1. Field of the Invention
The present invention relates to a voltage regulator configured to generate a constant output voltage based on an input voltage, and more particularly, to a technology for suppressing overshoot of an output voltage.
2. Description of the Related Art
In general, a voltage regulator is configured to generate a constant output voltage Vout at an output terminal based on an input voltage Vin that is input to an input terminal.
FIG. 2 is a circuit diagram of a related-art voltage regulator.
A bleeder resistor circuit 24 is configured to divide the output voltage Vout to generate a feedback voltage Vfb. A reference voltage circuit 23 is configured to output a reference voltage Vref. A differential amplifier 21 has an input terminal, to which the reference voltage Vref and the feedback voltage Vfb are input, and an output terminal connected to a gate of a MOS transistor 25. An output voltage detection circuit 26 has an input terminal connected to an output terminal of the voltage regulator, and an output terminal connected to a current source 22 configured to cause a bias current to flow through a differential amplifier 21.
Operation of the related-art voltage regulator is described.
When the reference voltage Vref is larger than the feedback voltage Vfb, an output of the differential amplifier 21 is low. Consequently, an ON resistance of the MOS transistor 25 becomes smaller, and the output voltage Vout of the voltage regulator thus becomes higher. That is, the voltage regulator is operated so that the feedback voltage Vfb and the reference voltage Vref may become equal to each other. When the feedback voltage Vfb is larger than the reference voltage Vref, operation reverse to the above-mentioned operation is performed, and hence the output voltage Vout becomes low. The voltage regulator is configured to keep the feedback voltage Vfb and the reference voltage Vref equal to each other all the time, to thereby output the constant output voltage Vout.
When the input voltage is transitionally increased, a gate voltage of the MOS transistor 25 follows the input voltage with a lag of time t, and hence a voltage difference between the gate voltage and a source voltage of the MOS transistor 25 is increased, with the result that overshoot occurs in the output voltage Vout of the voltage regulator.
The output voltage detection circuit 26 is configured to monitor the output voltage Vout. When overshoot occurs in the output voltage Vout, the output voltage detection circuit 26 outputs a detection signal to the current source 22 to cause the current source 22 to increase a bias current flowing through the differential amplifier 21. Thus, transient response characteristics of the differential amplifier 21 are improved, to thereby suppress the overshoot of the output voltage Vout (for example, see Japanese Patent Application Laid-open No. 2007-280025).
However, in the related-art voltage regulator, the gate voltage of the MOS transistor 25 is controlled with a higher voltage because the current of the current source 22 is increased.
Consequently, in the related-art voltage regulator, the gate voltage of the MOS transistor 25 is increased to be a steady operation voltage or more, and hence there is a problem in that undershoot occurs immediately after the overshoot is suppressed.